Alignment of samples across different clock domains

ABSTRACT

Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

This application is a continuation of U.S. patent application Ser. No. 15/239,591 entitled “ALIGNMENT OF SAMPLES ACROSS DIFFERENT CLOCK DOMAINS,” filed Aug. 17, 2016, which is incorporated herein by reference in its entirety.

FIELD

Embodiments relate generally to integrated circuits, and, more particularly, to techniques for aligning samples from different clock domains.

BACKGROUND

Performance of various types of circuits in a microprocessor can be impacted by changes in characteristics of power to those circuits. Some microprocessors include one or more measurement circuits that can detect such power management issues and can attempt to mitigate related issues. In some such measurement circuits, it is desirable to obtain correlated sample measurements of voltage droop, period jitter, phase delay, and/or other power characteristics. However, such characteristics are typically sampled in different clock domains, and it can be difficult in certain implementations to obtain accurate sample measurements, while maintaining reliable sample correlation across the different clock domains.

BRIEF SUMMARY

Among other things, embodiments provide novel systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop and phase delay. Though embodiments are described with reference to phase delay, some implementations actually measure period jitter, which may or may not be correlated with phase delay. For example, embodiments can sample voltage droop (VD) of a circuit according to a first clock domain to generate a VD sample for each of multiple first clock unit intervals (CUIs), and a rolling code (e.g., a reflected binary code, or Gray code) can be sampled according to the first clock domain to generate a VCode sample associable with each VD sample. Phase delay (PD) of the circuit can be sampled according to a second clock domain to generate a PD sample for each of a plurality of second CUIs, and the rolling code can be sampled according to the second clock domain to generate a PCode sample associable with each PD sample. For each first CUI, the VD sample for the first CUI can be output as a synchronized VD output, the VCode associated with the VD output can be identified, one of the PD samples can be identified as having an associated PCode that matches the identified VCode, and the identified PD sample can be output as a synchronized PD output for the first CUI.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is described in conjunction with the appended figures:

FIG. 1 shows a block diagram of an illustrative inter-domain sample alignment environment, as a context for various embodiments;

FIG. 2 shows an illustrative circuit implementation of a synchronization system, according to various embodiments;

FIG. 3 shows example, simplified signals to illustrate timing for a configuration of the circuit of FIG. 2; and

FIG. 4 shows a flow diagram of an illustrative method for time-aligning samples across multiple clock domains, according to various embodiments.

In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

DETAILED DESCRIPTION

Performance of various types of circuits in a microprocessor (e.g., static random-access memory, SRAM) can be impacted by changes in characteristics of power to those circuits. For example, phase-locked looped (PLLs), and the like, can be distributed around a microprocessor, but the duty cycle, operating frequency, and/or other parameters of those circuits can be sensitive to power management issues, such as voltage droop, phase delay, and other characteristics of power distributed to circuits of the microprocessor. Some microprocessors include one or more measurement circuits (e.g., four, eight, or more such circuits, distributed around the microprocessor) that can detect such power management issues and can attempt to mitigate related issues.

In some such measurement circuits, it is desirable to obtain correlated sample measurements of voltage droop, phase delay, and/or other power characteristics. However, voltage droop is typically sampled according to one clock domain (e.g., a frequency-locked clock), and phase delay is typically sampled according to another clock domain (e.g., a phase-locked clock, or other domain that provides precisely fixed voltage control). For example, voltage droop measurements can be obtained by using a first clock to sample voltage of a particular signal in a circuit as the signal passes through multiple delay lines (e.g., 64 samples obtained at 64 repeaters, encoded into a 6-bit measurement value); and phase delay measurements can be obtained by using a second clock to sample the signal's phase. To obtain accurate phase delay measurements, the second clock can use precisely fixed voltage control (e.g., a stable voltage source), so that only period can jitter from other error sources. Accordingly, the first and second clocks are typically different types of clocks operating in different clock domains. These different clocking domains have conventionally been considered close enough (e.g., within three to ten cycles of each other) to provide sufficient sample correlation. However certain implementations are impractical without more reliable sample correlation across the different clock domains. For example, some power management measurement circuits include multi-stage latches (e.g., first-in-first-out (FIFO) queues, or the like) to avoid certain issues, such as meta-stability issues that can result from asynchronous events entering bi-stable components. Over the multiple latch stages, the different clock domains can cause a loss of sample time correlation between the voltage droop and phase delay samples.

Embodiments are described herein for providing reliable and precise sample alignment across different clock domains. For example, voltage droop (VD) samples can be obtained in a first (e.g., frequency-locked) clock domain in a manner that associates each obtained sample with a VD timecode sample also obtained in the first clock domain. Phase delay (PD) samples can be obtained in a second (e.g., phase-locked) clock domain in a manner that associates each obtained sample with a PD timecode sample also obtained in the second clock domain. The VD and PD samples can be correlated according to their respective associated VD and PD timecodes, thereby aligning the samples.

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention.

FIG. 1 shows a block diagram of an illustrative inter-domain sample alignment environment 100, as a context for various embodiments. As illustrated, a synchronizer system 110 can include a voltage droop (VD) measurement input 102, a VD clock input 104, a phase delay (PD) measurement input 106, a PD clock input 108, an aligned VD output 165, and an aligned PD output 175. The illustrative synchronization system 110 is described as operating to obtain VD samples according to a first clock domain, to obtain PD samples according to a second clock domain, and to transfer the PD samples to the first clock domain to time-align the VD and PD samples. It will be appreciated that the described embodiments can be adapted to transfer VD samples to the second clock domain and/or to time-align any suitable types of samples from any suitable number of clock domains into any one of multiple clock domains.

As illustrated, the synchronization system 110 can include a voltage droop (VD) sampler structure 120 coupled with (or having) the VD clock input 104 and the VD measurement input 102, and having a VD sample output. The VD clock input 104 can be coupled with a first clock 185 operating in a first clock domain. For example, the first clock 185 can generate a first clock signal in the first clock domain according to a frequency-locked loop (FLL), or the like. The VD measurement input 102 can be coupled with a VD measurement system 180. The VD measurement system 180 can measure circuit signal voltage droop in any suitable manner. For example, the VD measurement system 180 can include delay lines (e.g., repeaters), and voltage samples can be recorded across the delay lines and encoded into a voltage droop measurement output. The VD measurement output can be coupled with the VD measurement input 102 of the synchronization system. The VD sample output can correspond to the VD measurement input 102 sampled at a corresponding VD sample time according to the VD clock input 104. For example, the VD sampler structure 120 can output a VD sample at each clock unit interval (CUI) of the first clock 185.

Embodiments of the synchronization system 110 also include a PD sampler structure 130 coupled with (or having) the PD clock input 108 and the PD measurement input 106, and having a PD sample output. The PD clock input 108 can be coupled with a second clock 195 operating in a second clock domain. For example, the second clock 195 can generate a second clock signal in the second clock domain according to a phase-locked loop (PLL), or the like. Typically, the second clock signal is generated with precisely fixed voltage control to help ensure precise phase measurement. The PD measurement input 106 can be coupled with a PD measurement system 190. The PD measurement system 190 can measure circuit signal phase delay in any suitable manner, for example as movement from a controlled phase reference. The PD sample output can correspond to the PD measurement input 106 sampled at a corresponding PD sample time according to the PD clock input 108. For example, the PD sampler structure 130 can output a PD sample at each clock unit interval (CUI) of the second clock 195.

As described above, the first clock domain is assumed to be different from the second clock domain, and the VD sample output and the PD sample output are assumed to be un-aligned with respect to time (the two clock domains may be close, but still asynchronous with respect to each other). Embodiments of the synchronization system 110 can also include a code generator (CG) structure 140 having a CG clock input coupled with the PD clock input 108 (or otherwise clocked according to the second clock domain in any suitable manner). The CG structure 140 can also include a code output generated at each CUI of the CG clock input. The code output can generally be any suitable code for providing correlation, as described below. For example, the CG structure 140 can include a rolling code generator with enough bits to ensure that each location in a storage array (as described below) can be associated with a unique one of the code outputs. In one implementation, the CG structure 140 includes a reflected binary code generator that outputs a rolling sequence of codes, where each code output differs from the preceding code output by only one bit. A new code output is effectively generated for each CUI of the second clock 195.

Embodiments of the PD sampler structure 130 can include, or be coupled with, a PD sample storage array 170 that operates to store each PD sample output in a respective storage location (e.g., a random access type of storage, where each location corresponds to a possible code output). For example, the storage array can include M storage locations, which can be successively used to store MPD sample outputs, which can be replaced successively by next PD sample outputs. The PD sample storage array 170 can have an index input coupled with the code output of the CG structure 140. For example, for each CUI of the PD clock input 108 (the second clock 195), a PD sample output is received from the PD sampler structure 130, and a code output is received from the CG structure 140; and the received PD sample output is stored in a location of the PD sample storage array 170 in association with the corresponding received code output. In one implementation, each location of the PD sample storage array 170 can be pre-associated with one of multiple possible code output values, and the received PD sample output can be stored in one of the locations selected according to the received code output. In another implementation, the code output can be stored as an index with the stored PD sample output.

Embodiments of the synchronization system 110 can also include a code synchronizer (CS) structure 150 having a CS clock input coupled with (or otherwise time-synchronized with) the VD clock input 104, a code input coupled with the code output, a code sample output, and a code synch output. The code sample output corresponds, at any VD sample time, to the code input sampled at the VD sample time according to the CS clock input. For example, for each CUI of the VD clock input 104 (the first clock 185), the CS structure 150 can output a sample of the code output generated by the CG structure 140. Thus, the code output is effectively a code corresponding to each second CUI, and the code sample output is effectively a sample of that code corresponding to each first CUI.

Circuits having bi-stable components that receive asynchronous events can potentially enter meta-stable states, which can be undesirable. To avoid such meta-stability, outputs can be passed through a multi-stage latch (e.g., to encourage settling). Accordingly, embodiments of the synchronization system 110 can include a VD sample latch 160. As used herein, “latch” is intended generally to include any suitable circuit for temporarily storing sample values according to an input clock, such as one or more flip-flops, or the like. As illustrated, each can be clocked according to the VD clock input 104 (the first clock 185), and can include a queue with an input stage, an output stage, and any suitable number of intermediate stages (e.g., 0 through N). Typically, where there are M locations in the PD sample storage array 170 and N latch stages, N is selected to be less than M. The input stage of the VD sample latch 160 can be coupled with the VD sample output of the VD sampler structure 120; so that when the output of the VD sample latch 160 corresponds to the VD sample output at sample time T_(S) (corresponding to a particular CUI of the VD clock input 104), the input of the VD sample latch 160 corresponds to the VD sample output at sample time T_(S+N), where there are N latch stages.

Similarly, embodiments of the CS structure 150 can include a multi-stage CS latch to correspond to synchronize the code samples with the VD samples as they propagate through the VD sample latch 160. The input stage of the CS latch can be coupled with the code sample output of the CS structure 150; so that when the output of the CS latch corresponds to the CS output at sample time T_(S) (corresponding to a particular CUI of the VD clock input 104), the input of the CS latch corresponds to the CS output at sample time T_(S+N) (N CUIs later), where there are N latch stages. The output of the CS latch can be the code synch output of the CS structure 150. Embodiments of the VD sample latch 160 and the CS latch can include the same number of stages, so that the output of the VD sample latch 160 and the code synch output correspond to a same sample time.

In some embodiments, the aligned VD output 165 is coupled with the output of the VD sample latch 160; and the aligned PD output 175 is coupled with the PD sample storage array 170. The PD sample storage array 170 is further coupled with the code synch output (the output of the CS latch). Effectively, at any particular sample time in the second clock domain (T_(P)), a sample of the phase delay measurement (from the PD measurement input 106) is stored in the PD sample storage array 170 in association with a generated code (from the CG structure 140) corresponding to that sample time. If there is a concurrent sample time in the first clock domain (T_(V)), a sample of the voltage droop measurement (from the VD measurement input 102) and a sample of the generated code (from the CG structure 140) for that time are obtained. Notably, the sample of the generated code at T_(V) (associated with the VD sample output for T_(S1)) will be a sample of the code generated for concurrent T_(P) (which is effectively the index stored with the PD sample output obtained for T_(P)). Embodiments use the code synch output as an index to select one of the stored PD samples in the PD sample storage array 170, which can then be output from the PD sample storage array 170 as the aligned PD output 175. Thus, the aligned PD output 175 corresponds to the code output that also corresponds to the aligned VD output 165 (i.e., to the VD sample output received concurrently with the PD sample output stored in the selected location of the PD sample storage array 170.

FIG. 2 shows an illustrative circuit implementation of a synchronization system 200, according to various embodiments. The synchronization system 200 can be an implementation of the synchronization system 110 of FIG. 1 and is labeled with corresponding reference designators for the sake of added clarity. The synchronization system 200 can have various inputs and outputs that can be coupled to external components. For example, a VD clock input 104 and a PD clock input 108 can be coupled with a first clock 185 and a second clock 195, respectively; and a VD measurement input 102 and a PD measurement input 106 can be coupled with a VD measurement system 180 and a PD measurement system 190, respectively.

The illustrated synchronization system 200 is designed to select between multiple configurations. In some implementations, only one configuration is used operationally, and the other configurations are provided for testing purposes. In other implementations, some or all configurations can be used operationally, invoked during diagnostic routines, used during chip testing phases, and/or in any other suitable manner. For example, as shown, each of the VD sampler structure 120 and the PD sampler structure 130 are coupled via a multiplexer, to either the VD clock input 104 (from the first clock 185) or the PD clock input 108 (from the second clock 195), selectable by signals “v_clk_sel” and “p_clk_sel”, respectively. Similarly, the PD sample storage array 170 can be selectively coupled to the VD clock input 104 or the PD clock input 108, depending on which clocks are selected for the VD sampler structure 120 and the PD sampler structure 130. Other components, however, such as the VD sample latch 160 and the CS latch of the CS structure 150, are shown coupled to the VD clock input 104 only (not selectable). Some implementations couple the CG structure 140 only to the PD clock input 108.

In a first configuration, the multiplexers are set so that the VD sampler structure 120 is clocked according to the VD clock input 104 (the first clock domain), and the PD sampler structure 130 is clocked according to the PD clock input 108 (the second clock domain). For added clarity, this first configuration is described with reference to FIG. 2 and to FIG. 3. FIG. 3 shows example, simplified signals 300 to illustrate timing for such a configuration. In this configuration, other multiplexers are set so that the VD sample output is coupled with the VD sample latch 160, and the PD sample output is coupled with the PD sample storage array 170.

As described with reference to FIG. 1, at a first sample time of the first clock 185 T_(V1) (e.g., a rising edge, a falling edge, etc.), the VD sampler structure 120 can output a first VD sample (VD₁) to an input stage (first flip-flop) of a VD sample latch 160 (shown as a three-stage latch). At a second sample time of the first clock 185 T_(V2), the VD sampler structure 120 can output a second VD sample (VD₂) to the input stage of the VD sample latch 160, and VD₁ can propagate to the second stage of the latch. This can continue, so that, at any given sample time of the first clock 185 T_(VS), the input stage (labeled “AA”) of the VD sample latch 160 indicates a present VD sample VD_(S), and the output stage (labeled “AAA”) of the VD sample latch 160 indicates a past VD sample VD_(S−2). For example, FIG. 3 indicates that the output of the VD sample latch 160 (AAA, which can be aligned VD output 165) corresponds to the input of the VD sample latch 160 (AA, which is labeled as 102′) from three samples earlier of the VD clock input 104 (for a 3-stage latch).

The code synchronizer (CS) structure 150 can operate in a similar manner to the VD sample latch 160. For example, at any given sample time of the first clock 185 T_(VS), the input stage (labeled “BB”) of the CS structure 150 latch indicates a present code sample C_(S), and the output stage (labeled “BBB”) of the CS structure 150 latch indicates a past code sample C_(S−2). Notably, the output at AAA and BBB correspond to a same sample time T_(VS-2). With reference to FIG. 1, the output at AAA can be the aligned VD output 165, and the output at BBB can be the code synch output. For example, FIG. 3 indicates that the output of the CS structure 150 (BBB, which can be the code synch output, and is labeled 320) corresponds to the input of the CS structure 150 (BB, which is labeled as 315) from three samples earlier of the VD clock input 104 (for a 3-stage latch). As shown in FIG. 3, VD₁ was sampled in the same sample time of the first clock 185 as was the code ‘011’; and VD₂ was sampled in the same sample time of the first clock 185 as was the code ‘000’.

In the first configuration, the PD sample storage array 170 a is configured to be clocked according to the PD clock input 108 (the second clock domain) and to receive PD sample outputs (also clocked according to the PD clock input 108) from the PD sampler structure 130. Two instances of the PD sample storage array 170 a,b are shown to facilitate different configurations, as described below. The PD sample storage arrays 170 are shown as random access arrays of storage locations indexed by possible code output values. At any particular time (e.g., after the eight flip flop locations are filled), each of the flip flops of the PD sample storage array 170 a has a PD sample stored in association with a code output corresponding to the sample time at which the PD sample was obtained. The output of the PD sample storage array 170 a (labeled as “CCC”) corresponds to the PD sample stored in whichever location is also storing the code output that matches the code synch output (from BBB). The output at CCC can be the aligned PD output 175. As described above, in this way, the aligned PD output 175 and the aligned VD output 165 can effectively be time-aligned via the corresponding code value. As described above, using a multi-stage latch for the VD sample latch 160 (and for the CS structure 150) can help avoid meta-stability issues in the PD sample storage array 170. Typically, the number of flip flops in the PD sample storage array 170 (M) is designed to be larger than the number of stages in the VD sample latch 160 (N).

For example, FIG. 3 indicates that, at each sample time of the PD clock input 108, a PD sample is recorded (indicated over time as 106′) and an associated code output is recorded (indicated over time as 305) at the input to the PD sample storage array 170. As described above, the code output can be any suitable code, such as a Gray code (signal 305 is intended as one illustrative type of code). The output of the PD sample storage array 170 (CCC, which can be aligned PD output 175) corresponds to whichever PD sample is associated with the code output that matched the code synch output. As shown, the code synch output corresponding to the sample time for VD₁ is ‘011’, which corresponds to the storage location of PD₁; and the code synch output corresponding to the sample time for VD₂ is ‘000’, which corresponds to the storage location of PD₃. Thus, the aligned VD output 165 (VD₁, VD₂, etc.) is time-aligned with the aligned PD output 175 (PD₁, PD₃, etc.).

In a second configuration of the synchronization system 200, both the VD sampler structure 120 and the PD sampler structure 130 can be coupled (via the multiplexers) to the VD clock input 104. In such a configuration, no synchronization is needed, as the samples are clocked in the same clock domain. In some such implementations, output multiplexers 220 can be set to select directly from the VD sample output and the PD sample output, effectively bypassing the synchronization system 200.

In a third configuration of the synchronization system 200, the multiplexers can be configured to couple the VD sampler structure 120 with the PD clock input 108 and the PD sampler structure 130 with the VD clock input 104 (i.e., swapping clock domains). Input multiplexers 210 can be set, so that the PD sample output is coupled into the VD sample latch 160 (to AA), and the VD sample output is coupled into the PD sample storage array 170 (to CC). The output multiplexers 220 can be set to effectively swap the outputs of the VD sample latch 160 and the PD sample storage array 170 (e.g., the aligned VD output 165 and the aligned PD output 175 are effectively swapped to become the aligned PD output 175 and the aligned VD output 165, respectively).

In a fourth configuration of the synchronization system 200, the both the VD sampler structure 120 and the PD sampler structure 130 can be coupled (via the multiplexers) to the PD clock input 108. In such a configuration, input multiplexers 210 can be set, so that the VD sample output is coupled into the first PD sample storage array 170 a (to CC), and the PD sample output is coupled into the second PD sample storage array 170 b (to DD). The output multiplexers 220 can be set to effectively read out and swap the outputs of the two PD sample storage arrays 170 (e.g., the output of the first PD sample storage array 170 a effectively becomes the aligned VD output 165, and the output of the second PD sample storage array 170 b effectively becomes the aligned PD output 175).

The various illustrated configurations are intended only as examples. The illustrated synchronization system 200 is designed to have particular configurations determined to provide operational and diagnostic value without overcomplicating the design. For example, the fourth configuration can alternatively be designed to operate more like the second configuration.

FIG. 4 shows a flow diagram of an illustrative method 400 for time-aligning samples across multiple clock domains, according to various embodiments. Embodiments begin at stage 404 by sampling voltage droop (VD) of a circuit according to a first clock domain to generate a VD sample for each of multiple first clock unit intervals (CUIs). At stage 408, a rolling code can be sampled according to the first clock domain to generate a VCode sample associable with each VD sample. The rolling code can be generated according to a second clock domain as a PCode for each of multiple second CUIs. At stage 412, phase delay (PD) of the circuit can be sampled according to the second clock domain to generate a PD sample for each of the multiple second CUIs, so that each PD sample is associable with the PCode for its second CUI. Embodiments can proceed with stages 420-432 for any particular one (e.g., all) of the first CUIs. At stage 420, embodiments can output the VD sample for the first CUI as an aligned VD output. At stage 424, the VCode associated with the VD output can be identified; and, at stage 428, one of the PD samples can be identified as having an associated PCode that matches the identified VCode. At stage 432, the identified PD sample can be output as an aligned PD output for the first CUI.

Though embodiments are described with reference to voltage droop and phase delay, similar techniques can be used in context of any suitable types of first and second samples in first and second clock domains. For example, embodiments can include any suitable means for generating code synch samples of a rolling code according to a first clock domain, each rolling code generated to correspond to a second clock domain sample time, such that each code synch sample corresponds to a first clock domain sample time and indicates the rolling code generated for the second clock domain sample time that coincides with the corresponding first clock domain sample time. As described herein, such means can include any suitable code generator structure (e.g., including a reflected binary code generator, or the like) and any suitable code synchronizer structure (e.g., including a multi-stage latch, or the like).

Embodiments can also include means for outputting one of a number of first samples, the first samples generated according to the first clock domain, such that the output first sample corresponds to a first clock domain sample time that corresponds to one of the code synch samples. For example, such means can include any suitable sampling structure for sampling measured or other output, latch for holding the samples (e.g., and synchronizing, delaying, etc., as desired), etc. Some such means can further include one or more measurement systems for generating the measurements and/or one or more clocks for generating clock signals according to the first clock domain.

Embodiments can also include means for outputting one of multiple second samples, the second samples generated according to the second clock domain, such that each second sample corresponds to a second clock domain sample time and is associated with the rolling code generated for the corresponding second clock domain sample time, the output second sample being selected from second samples as being associated with the rolling code that matches the one of the code synch samples corresponding to the output first sample. For example, such means can include any suitable sampling structure for sampling measured or other output, storage array for holding the samples in association with rolling code indexes, etc. Some such means can further include one or more measurement systems for generating the measurements and/or one or more clocks for generating clock signals according to the second clock domain. The various means described above can further include multiplexers and or other components for changing the configuration of the system, as desired (e.g., as described with reference to FIG. 2).

The methods disclosed herein comprise one or more actions for achieving the described method. The method and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claims.

The steps of a method or algorithm or other functionality described in connection with the present disclosure, may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of tangible storage medium. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM and so forth. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. A software module may be a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. Thus, a computer program product may perform operations presented herein. For example, such a computer program product may be a computer readable tangible medium having instructions tangibly stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. The computer program product may include packaging material. Software or instructions may also be transmitted over a transmission medium. For example, software may be transmitted from a website, server, or other remote source using a transmission medium such as a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, or microwave.

Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of” indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Further, the term “exemplary” does not mean that the described example is preferred or better than other examples.

Various changes, substitutions, and alterations to the techniques described herein can be made without departing from the technology of the teachings as defined by the appended claims. Moreover, the scope of the disclosure and claims is not limited to the particular aspects of the process, machine, manufacture, composition of matter, means, methods, and actions described above. Processes, machines, manufacture, compositions of matter, means, methods, or actions, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein may be utilized. Accordingly, the appended claims include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or actions. 

What is claimed is:
 1. A synchronizer system for aligning power management data from multiple clock domains in measurement circuits, comprising: a first power management characteristic (PMC) sampler receiving a first clock input clocked according to a first clock domain and further receiving a first PMC measurement input in the first clock domain, wherein the first PMC sampler generates a first PMC output in the first clock domain, wherein the first PMC output comprises a first PMC sample of the first PMC measurement input associated with a code; and a second PMC sampler receiving a second clock input clocked according to a second clock domain and further receiving a second PMC measurement input in the second clock domain, wherein the second PMC sampler generates a second PMC output comprising a second PMC sample of the second PMC measurement input associated with the code, wherein the second PMC output is synchronized to the first clock domain as a function of being associated with the code.
 2. The synchronizer system of claim 1, further comprising: a code synchronizer (CS) structure synchronized to the first clock domain, wherein the CS structure outputs the code corresponding to a first PMC sample time of the first PMC sample; and a storage array coupled to the CS structure to receive the code from the CS structure, wherein the second PMC sampler stores the second PMC sample in the storage array in association with the code.
 3. The synchronizer system of claim 2, further comprising a first latch operable to temporarily retain the first PMC sample such that the first PMC output from the first latch is synchronized with the second PMC output from the storage array.
 4. The synchronizer system of claim 3, further comprising a code generator coupled to the CS structure and the storage array, wherein the code generator generates a rolling code and wherein the code is a sample of the rolling code.
 5. The synchronizer system of claim 4, further comprising a second latch coupled to the CS structure to delay transmission of the code from the CS structure to the storage array to synchronize the second PMC output from the storage array with the first PMC output from the first latch.
 6. The synchronizer system of claim 5, wherein: the first clock domain is maintained by a frequency-locked loop; the second clock domain is maintained by a phase-locked loop; the first PMC is voltage droop; and the second PMC is phase delay.
 7. The synchronizer system of claim 5, wherein: the first clock domain is maintained by a phase-locked loop; the second clock domain is maintained by a frequency-locked loop; the first PMC is phase delay; and the second PMC is voltage droop.
 8. The synchronizer system of claim 2, wherein the first PMC output from the first PMC sampler is synchronized with the second PMC output from the storage array.
 9. The synchronizer system of claim 8, further comprising a code generator coupled to the CS structure and the storage array, wherein the code generator generates a rolling code and wherein the code is a sample of the rolling code.
 10. The synchronizer system of claim 9, further comprising a second latch coupled to the CS structure to delay transmission of the code from the CS structure to the storage array to synchronize the second PMC output from the storage array with the first PMC output from the first PMC sampler.
 11. The synchronizer system of claim 10, wherein: the first clock domain is maintained by a frequency-locked loop; the second clock domain is maintained by a phase-locked loop; the first PMC is voltage droop; and the second PMC is phase delay.
 12. The synchronizer system of claim 10, wherein: the first clock domain is maintained by a phase-locked loop; the second clock domain is maintained by a frequency-locked loop; the first PMC is phase delay; and the second PMC is voltage droop.
 13. A method for aligning samples across multiple clock domains, the method comprising: sampling a first power management characteristic (PMC) of a circuit at a first time according to a first clock domain to generate a first PMC sample; first sampling a rolling code according to the first clock domain to generate a first code corresponding to the first time, the rolling code generated according to a second clock domain; sampling a second PMC of the circuit at a second time according to the second clock domain to generate a second PMC sample; second sampling the rolling code according to the second clock domain to generate a second code corresponding to the second time; and synchronously outputting the first PMC sample as a first PMC output and the second PMC sample as a second PMC output based on the second code matching the first code.
 14. The method of claim 13, wherein: the first sampling is performed at a code synchronizer (CS) structure; and the second sampling is performed at a storage array.
 15. The method of claim 14, further comprising: queueing the first PMC sample in a first latch for delayed output.
 16. The method of claim 15, further comprising: queueing the first code in a second latch for delayed transmission from the CS structure to the storage array at a third time, wherein the first PMC sample is output at the third time.
 17. The method of claim 16, further comprising: maintaining the first clock domain using a frequency-locked loop; maintaining the second clock domain using a phase-locked loop; wherein the first PMC is voltage droop and the second PMC is phase delay.
 18. The method of claim 13, further comprising: maintaining the first clock domain using a phase-locked loop; maintaining the second clock domain using a frequency-locked loop; wherein the first PMC is phase delay and the second PMC is voltage droop.
 19. An integrated circuit comprising: a first synchronizer system for aligning power management data from multiple clock domains in measurement circuits; and a second synchronizer system for aligning power management data from multiple clock domains in measurement circuits, wherein the second synchronizer system comprises: a first power management characteristic (PMC) sampler receiving a first clock input clocked according to a first clock domain and further receiving a first PMC measurement input in the first clock domain, wherein the first PMC sampler then outputs a first PMC output in the first clock domain, wherein the first PMC output comprises a first PMC sample of the first PMC measurement input associated with a code; and a second PMC sampler receiving a second clock input clocked according to a second clock domain and further receiving a second PMC measurement input in the second clock domain, wherein the second PMC sampler then outputs a second PMC output comprising a second PMC sample of the second PMC measurement input associated with the code, wherein the second PMC output is synchronized to the first clock domain as a function of being associated with the code.
 20. The integrated circuit of claim 19, wherein the second synchronizer system further comprises: a code synchronizer (CS) structure synchronized to the first clock domain, wherein the CS structure outputs the code corresponding to a first PMC sample time of the first PMC sample; a storage array coupled to the CS structure to receive the code from the CS structure, wherein the second PMC sampler stores the second PMC sample in the storage array in association with the code; a first latch operable to temporarily retain the first PMC sample such that the first PMC output from the first latch is synchronized with the second PMC output from the storage array; a code generator coupled to the CS structure and the storage array, wherein the code generator generates a rolling code and wherein the code is a sample of the rolling code; and a second latch coupled to the CS structure to delay transmission of the code from the CS structure to the storage array to synchronize the second PMC output from the storage array with the first PMC output from the first latch; wherein: the first clock domain is maintained by a frequency-locked loop; the second clock domain is maintained by a phase-locked loop; the first PMC is voltage droop; and the second PMC is phase delay. 